CPU_test_bench.vhd

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-- Company: 
-- Engineer:
--
-- Create Date:   23:20:05 11/03/2023
-- Design Name:   
-- Module Name:   /home/student2/aszava/Desktop/COE 758/Project 1/cacheController2/CPU_test_bench.vhd
-- Project Name:  cacheController2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: CPU_gen
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY CPU_test_bench IS
END CPU_test_bench;
 
ARCHITECTURE behavior OF CPU_test_bench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT CPU_gen
    PORT(
         clk : IN  std_logic;
         rst : IN  std_logic;
         trig : IN  std_logic;
         Address : OUT  std_logic_vector(15 downto 0);
         wr_rd : OUT  std_logic;
         cs : OUT  std_logic;
         DOut : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
   signal trig : std_logic := '0';

 	--Outputs
   signal Address : std_logic_vector(15 downto 0);
   signal wr_rd : std_logic;
   signal cs : std_logic;
   signal DOut : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: CPU_gen PORT MAP (
          clk => clk,
          rst => rst,
          trig => trig,
          Address => Address,
          wr_rd => wr_rd,
          cs => cs,
          DOut => DOut
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;
		rst <= '1';
		trig <= '0';
		
		wait for clk_period*4;
		
		rst <= '0';
		trig <= '1';
		
		wait for clk_period*1;
		
		trig <= '0';
		
		wait for clk_period*4;
		
		rst <= '0';
		trig <= '1';
		
		wait for clk_period*1;
		
		trig <= '0';
		
		wait for clk_period*4;

		rst <= '0';
		trig <= '1';
		
		wait for clk_period*1;
		
		trig <= '0';
		
		wait for clk_period*4;

      -- insert stimulus here 

      wait;
   end process;

END;