fsm_test_bench.vhd

--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   19:20:13 11/03/2023
-- Design Name:   
-- Module Name:   /home/student2/aszava/Desktop/COE 758/Project 1/cacheController2/fsm_test_bench.vhd
-- Project Name:  cacheController2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: ctrl_fsm
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY fsm_test_bench IS
END fsm_test_bench;
 
ARCHITECTURE behavior OF fsm_test_bench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT ctrl_fsm
    PORT(
         tag : IN  std_logic_vector(7 downto 0);
         old_tag : IN  std_logic_vector(7 downto 0);
         index : IN  std_logic_vector(2 downto 0);
         offset : IN  std_logic_vector(4 downto 0);
         clk : IN  std_logic;
         MSTRB : OUT  std_logic;
         dirty : IN  std_logic;
         hit : IN  std_logic;
         cs : IN  std_logic;
         WR_RDi : IN  std_logic;
         RDY : OUT  std_logic;
         Addr_out : OUT  std_logic_vector(15 downto 0);
         WEN : OUT  std_logic_vector(0 downto 0);
         Dout_sel : OUT  std_logic;
         Din_sel : OUT  std_logic;
         WR_RDo : OUT  std_logic;
         table_WEN : OUT  std_logic;
         data_to_table : OUT  std_logic_vector(9 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal tag : std_logic_vector(7 downto 0) := (others => '0');
   signal old_tag : std_logic_vector(7 downto 0) := (others => '0');
   signal index : std_logic_vector(2 downto 0) := (others => '0');
   signal offset : std_logic_vector(4 downto 0) := (others => '0');
   signal clk : std_logic := '0';
   signal dirty : std_logic := '0';
   signal hit : std_logic := '0';
   signal cs : std_logic := '0';
   signal WR_RDi : std_logic := '0';

 	--Outputs
   signal MSTRB : std_logic;
   signal RDY : std_logic;
   signal Addr_out : std_logic_vector(15 downto 0);
   signal WEN : std_logic_vector(0 downto 0);
   signal Dout_sel : std_logic;
   signal Din_sel : std_logic;
   signal WR_RDo : std_logic;
   signal table_WEN : std_logic;
   signal data_to_table : std_logic_vector(9 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: ctrl_fsm PORT MAP (
          tag => tag,
          old_tag => old_tag,
          index => index,
          offset => offset,
          clk => clk,
          MSTRB => MSTRB,
          dirty => dirty,
          hit => hit,
          cs => cs,
          WR_RDi => WR_RDi,
          RDY => RDY,
          Addr_out => Addr_out,
          WEN => WEN,
          Dout_sel => Dout_sel,
          Din_sel => Din_sel,
          WR_RDo => WR_RDo,
          table_WEN => table_WEN,
          data_to_table => data_to_table
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;

		wait for clk_period*10;

      tag <= "00001111";
		index <= "010";
		offset <= "11011";
		dirty <= '1';
		hit <= '0';
		cs <= '1';
		WR_RDi <= '1';
		
		wait for clk_period*4;
		cs <= '0';

      wait;
   end process;

END;