project_test_bench.vhd

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-- Company: 
-- Engineer:
--
-- Create Date:   00:25:16 11/04/2023
-- Design Name:   
-- Module Name:   /home/student2/aszava/Desktop/COE 758/Project 1/cacheController2/project_test_bench.vhd
-- Project Name:  cacheController2
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: project1
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY project_test_bench IS
END project_test_bench;
 
ARCHITECTURE behavior OF project_test_bench IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT project1
    PORT(
         inClock : IN  std_logic;
         cpu_trig : IN  std_logic;
         CPU_reset : IN  std_logic;
         db_ready : OUT  std_logic;
         db_din_to_cpu : OUT  std_logic_vector(7 downto 0);
         db_addr_from_cpu : OUT  std_logic_vector(15 downto 0);
         db_wr_rd_from_cpu : OUT  std_logic;
         db_cs_from_cpu : OUT  std_logic;
         db_dout_from_cpu : OUT  std_logic_vector(7 downto 0);
         db_addr_to_mem : OUT  std_logic_vector(15 downto 0);
         db_wr_rd_to_mem : OUT  std_logic;
         db_memstrb : OUT  std_logic;
         db_data_to_mem : OUT  std_logic_vector(7 downto 0);
         db_data_from_mem : OUT  std_logic_vector(7 downto 0);
			db_addr_to_sram : OUT std_logic_vector(7 downto 0);
			db_mode : in std_logic;
			db_state : out std_logic_vector(2 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal inClock : std_logic := '0';
   signal cpu_trig : std_logic := '0';
   signal CPU_reset : std_logic := '0';
	signal db_mode : std_logic;


 	--Outputs
   signal db_ready : std_logic;
   signal db_din_to_cpu : std_logic_vector(7 downto 0);
   signal db_addr_from_cpu : std_logic_vector(15 downto 0);
   signal db_wr_rd_from_cpu : std_logic;
   signal db_cs_from_cpu : std_logic;
   signal db_dout_from_cpu : std_logic_vector(7 downto 0);
   signal db_addr_to_mem : std_logic_vector(15 downto 0);
   signal db_wr_rd_to_mem : std_logic;
   signal db_memstrb : std_logic;
   signal db_data_to_mem : std_logic_vector(7 downto 0);
   signal db_data_from_mem : std_logic_vector(7 downto 0);
	signal db_addr_to_sram : std_logic_vector(7 downto 0);
	signal db_state : std_logic_vector(2 downto 0);

   -- Clock period definitions
   constant inClock_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: project1 PORT MAP (
          inClock => inClock,
          cpu_trig => cpu_trig,
          CPU_reset => CPU_reset,
          db_ready => db_ready,
          db_din_to_cpu => db_din_to_cpu,
          db_addr_from_cpu => db_addr_from_cpu,
          db_wr_rd_from_cpu => db_wr_rd_from_cpu,
          db_cs_from_cpu => db_cs_from_cpu,
          db_dout_from_cpu => db_dout_from_cpu,
          db_addr_to_mem => db_addr_to_mem,
          db_wr_rd_to_mem => db_wr_rd_to_mem,
          db_memstrb => db_memstrb,
          db_data_to_mem => db_data_to_mem,
          db_data_from_mem => db_data_from_mem,
			 db_mode => db_mode,
			 db_addr_to_sram => db_addr_to_sram,
			 db_state => db_state
        );

   -- Clock process definitions
   inClock_process :process
   begin
		inClock <= '0';
		wait for inClock_period/2;
		inClock <= '1';
		wait for inClock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for inClock_period*10;

      cpu_reset <= '1';
		cpu_trig <= '0';
		db_mode <= '0';
		
		wait for inClock_period*4;
		
		cpu_reset <= '0';
		cpu_trig <= '1';
		
		wait for inClock_period;
		
		cpu_trig <= '0';
		db_mode <= '1';
		
		
      wait;
   end process;

END;