Cleanup for Dart 3.8 (#52)

Author: mkorbel1

.github/workflows/general.yml

@@ -33,8 +33,6 @@ jobs:
 
       - name: Setup Dart
         uses: dart-lang/setup-dart@v1
-        with:
-          sdk: 3.6.2 # downgrade pending https://github.com/dart-lang/dartdoc/issues/3996
 
       - name: Install Dart dependencies
         run: tool/gh_actions/install_dart_dependencies.sh
@@ -92,8 +90,6 @@ jobs:
 
       - name: Setup Dart
         uses: dart-lang/setup-dart@v1
-        with:
-          sdk: 3.6.2 # downgrade pending https://github.com/dart-lang/dartdoc/issues/3996
 
       - name: Install dart dependencies
         run: tool/gh_actions/install_dart_dependencies.sh

lib/src/configs/cosim_process_config.dart

@@ -84,8 +84,8 @@ abstract class CosimProcessConfig extends CosimConfig {
       outFileSink?.write(message);
     }
 
-    unawaited(procFuture.then((proc) {
-      proc.stdout.transform(utf8.decoder).forEach((msg) async {
+    unawaited(procFuture.then((proc) async {
+      unawaited(proc.stdout.transform(utf8.decoder).forEach((msg) async {
         Cosim.logger?.finest('SIM STDOUT:\n$msg');
         cosimLog(msg);
 
@@ -98,14 +98,14 @@ abstract class CosimProcessConfig extends CosimConfig {
             socketConnectionCompleter.complete();
           }
         }
-      });
+      }));
 
-      proc.stderr.transform(utf8.decoder).forEach((msg) {
+      unawaited(proc.stderr.transform(utf8.decoder).forEach((msg) {
         Cosim.logger?.warning('SIM STDERR:\n$msg');
         cosimLog(msg);
-      });
+      }));
 
-      proc.exitCode.then((value) {
+      unawaited(proc.exitCode.then((value) {
         Cosim.logger?.fine('SIM EXIT CODE: $value');
 
         if (value != 0) {
@@ -122,7 +122,7 @@ abstract class CosimProcessConfig extends CosimConfig {
           }
           Cosim.endCosim();
         }
-      });
+      }));
     }));
 
     Cosim.logger?.finer('Waiting for socket to connect...');

lib/src/cosim.dart

@@ -366,12 +366,12 @@ mixin Cosim on ExternalSystemVerilogModule {
 
     _receivedStream
         .where((event) => event.cosimMessageType == _CosimMessageType.end)
-        .listen((event) {
+        .listen((event) async {
       logger?.info('Received an indication that the simulator has finished.');
       if (onEnd != null) {
         onEnd();
       }
-      Simulator.endSimulation();
+      unawaited(Simulator.endSimulation());
     });
 
     // set up initial values
@@ -392,7 +392,7 @@ mixin Cosim on ExternalSystemVerilogModule {
           continue;
         }
 
-        modInput.glitch.listen((event) {
+        modInput.glitch.listen((event) async {
           // TODO(mkorbel1): test for clock divider bug, https://github.com/intel/rohd-cosim/issues/6
 
           if (Simulator.phase != SimulatorPhase.clkStable) {
@@ -404,7 +404,7 @@ mixin Cosim on ExternalSystemVerilogModule {
             // driving it, so hold onto it for later
             registree._inputsPendingPostUpdate.add(modInput);
             if (!registree._pendingPostUpdate) {
-              Simulator.postTick.first.then((value) {
+              unawaited(Simulator.postTick.first.then((value) {
                 // once the tick has completed, we can update the override maps
                 for (final driverInput in registree._inputsPendingPostUpdate) {
                   registree._inputToPreTickInputValuesMap[driverInput] =
@@ -419,7 +419,7 @@ mixin Cosim on ExternalSystemVerilogModule {
                   await _sendPendingUpdates(
                       throwOnUnexpectedEnd: throwOnUnexpectedEnd);
                 });
-              });
+              }));
             }
             registree._pendingPostUpdate = true;
           }