Update CI configuration

Author: shashankov

.github/workflows/ci.yml

@@ -1,4 +1,4 @@
-name: NoC Regression CI
+name: Regression
 
 on:
   push:
@@ -13,7 +13,7 @@ jobs:
 
     steps:
       - name: Checkout Code
-        uses: actions/checkout@v4
+        uses: actions/checkout@v5
 
       - name: Set up Python
         uses: actions/setup-python@v5
@@ -27,10 +27,10 @@ jobs:
 
       - name: Cache Verilator Build
         id: cache-verilator
-        uses: actions/cache@v4
+        uses: actions/cache@v5
         with:
           path: /home/runner/verilator-bin
-          key: verilator-5.048-v1
+          key: verilator-5.048-v2
 
       - name: Install Build Prerequisites
         run: |
@@ -59,4 +59,4 @@ jobs:
 
       - name: Run Regression Suite
         run: |
-          make -C test regress REGRESS_PACKET_COUNT=65536
+          make -C test regress REGRESS_PACKET_COUNT=65536 THREADS=4

README.md

@@ -1,5 +1,10 @@
 # ReCONNECT: FPGA-Optimized RTL-Native Network-on-Chip (NoC)
 
+[![Regression](https://github.com/shashankov/ReCONNECT/actions/workflows/ci.yml/badge.svg)](https://github.com/shashankov/ReCONNECT/actions/workflows/ci.yml)
+[![License: MIT](https://img.shields.io/badge/License-MIT-yellow.svg)](https://opensource.org/licenses/MIT)
+[![Language](https://img.shields.io/badge/Language-SystemVerilog-blue.svg)](https://en.wikipedia.org/wiki/SystemVerilog)
+[![Simulators](https://img.shields.io/badge/Simulators-Verilator%20%7C%20ModelSim-purple.svg)](#)
+
 Author: Shashank Obla (https://www.andrew.cmu.edu/user/sobla)
 
 ReCONNECT is a highly-parametrizable, high-performance soft network-on-chip designed to be customizable to the needs of the application while being resource-minimal and tuned for modern FPGA architectures. Written directly in SystemVerilog (RTL), the NoC is specially optimized for high-frequency operations on Intel FPGA architectures (such as Intel Agilex 7) and operates at frequencies exceeding 500 MHz. Find more about it here: [https://www.andrew.cmu.edu/user/sobla/projects/noc/](https://www.andrew.cmu.edu/user/sobla/projects/noc/)

test/Makefile

@@ -2,7 +2,8 @@
 # Parameterized for any topology and config
 
 VERILATOR ?= verilator
-VERILATOR_FLAGS = --binary --top-module generic_harness_tb_sim -Wno-fatal -Wno-WIDTH -Wno-PINMISSING -Wno-IMPLICIT -DSIMULATION --threads 4
+THREADS ?= 4
+VERILATOR_FLAGS = --binary --top-module generic_harness_tb_sim -Wno-fatal -Wno-WIDTH -Wno-PINMISSING -Wno-IMPLICIT -DSIMULATION --threads $(THREADS)
 
 VSIM = vsim -c
 PYTHON ?= python3