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sylefebsylefeb
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wip: sdram playground, improvements
1 parent 8792b6c commit 1aced3c

2 files changed

Lines changed: 45 additions & 40 deletions

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‎projects/sdram_playground/pll.v‎

Lines changed: 16 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5,15 +5,16 @@
55
module pll
66
(
77
input clkin, // 25 MHz, 0 deg
8-
output clkout0, // 100 MHz, 0 deg
9-
output clkout1, // 100 MHz, 0 deg
8+
output clkout0, // 50 MHz, 0 deg
9+
output clkout1, // 25 MHz, 0 deg
1010
output clkout2, // 100 MHz, 0 deg
1111
output clkout3, // 100 MHz, 180 deg
12-
output locked
12+
output locked,
13+
output reset
1314
);
1415
(* FREQUENCY_PIN_CLKI="25" *)
15-
(* FREQUENCY_PIN_CLKOP="100" *)
16-
(* FREQUENCY_PIN_CLKOS="100" *)
16+
(* FREQUENCY_PIN_CLKOP="50" *)
17+
(* FREQUENCY_PIN_CLKOS="25" *)
1718
(* FREQUENCY_PIN_CLKOS2="100" *)
1819
(* FREQUENCY_PIN_CLKOS3="100" *)
1920
(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
@@ -28,23 +29,23 @@ EHXPLLL #(
2829
.OUTDIVIDER_MUXD("DIVD"),
2930
.CLKI_DIV(1),
3031
.CLKOP_ENABLE("ENABLED"),
31-
.CLKOP_DIV(6),
32-
.CLKOP_CPHASE(2),
32+
.CLKOP_DIV(12),
33+
.CLKOP_CPHASE(5),
3334
.CLKOP_FPHASE(0),
3435
.CLKOS_ENABLE("ENABLED"),
35-
.CLKOS_DIV(6),
36-
.CLKOS_CPHASE(2),
36+
.CLKOS_DIV(24),
37+
.CLKOS_CPHASE(5),
3738
.CLKOS_FPHASE(0),
3839
.CLKOS2_ENABLE("ENABLED"),
3940
.CLKOS2_DIV(6),
40-
.CLKOS2_CPHASE(2),
41+
.CLKOS2_CPHASE(5),
4142
.CLKOS2_FPHASE(0),
4243
.CLKOS3_ENABLE("ENABLED"),
4344
.CLKOS3_DIV(6),
44-
.CLKOS3_CPHASE(5),
45+
.CLKOS3_CPHASE(8),
4546
.CLKOS3_FPHASE(0),
4647
.FEEDBK_PATH("CLKOP"),
47-
.CLKFB_DIV(4)
48+
.CLKFB_DIV(2)
4849
) pll_i (
4950
.RST(1'b0),
5051
.STDBY(1'b0),
@@ -64,4 +65,7 @@ EHXPLLL #(
6465
.ENCLKOP(1'b0),
6566
.LOCK(locked)
6667
);
68+
69+
assign reset = ~locked;
70+
6771
endmodule

‎projects/sdram_playground/sdram_ctrl_test.si‎

Lines changed: 29 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -100,10 +100,10 @@ $$end
100100
{
101101

102102
$$if not ICARUS then
103-
uint1 rst = uninitialized;
104-
clean_reset rstcond<@sdram_clock,!reset> (
105-
out :> rst
106-
);
103+
uint1 rst(1);
104+
//clean_reset rstcond<@sdram_clock,!reset> (
105+
// out :> rst
106+
//);
107107
$$else
108108
uint1 sdram_clock(0);
109109
$$end
@@ -159,7 +159,8 @@ $$if ULX3S then
159159
clkout1 :> video_clock,
160160
clkout2 :> sdram_clock, // controller
161161
clkout3 :> sdram_clk, // chip
162-
locked :> pll_lock
162+
locked :> pll_lock,
163+
reset :> rst
163164
);
164165
$$end
165166
$$if DE10NANO then
@@ -241,9 +242,9 @@ $$end
241242
uint2 reg_sdram_dqm (0);
242243
uint2 reg_sdram_ba (0);
243244
uint13 reg_sdram_a (0);
244-
uint16 reg_dq_o (0);
245+
uint16 reg_dq_o = 0;
245246
uint3 tmp_dq_en (0);
246-
uint1 reg_dq_en (0);
247+
uint1 reg_dq_en = 0;
247248

248249
// SDRAM commands
249250
$$CMD_dummy_WAIT_init = '1111'
@@ -261,8 +262,8 @@ $$CMD_LOAD_MODE_REG = '0000'
261262
$$AddrZ = '0000000000000'
262263
$$AddrA_row = '0000000000000'
263264
$$AddrA_col = '0000000000000'
264-
$$AddrB_row = '0000000000010'
265-
$$AddrB_col = '0000000000000'
265+
$$AddrB_row = '0000000000000'
266+
$$AddrB_col = '0000000001000'
266267
$$Addr_wait_init = '1111111111111'
267268
$$Addr_wait_2 = '0000000000000' -- value are delay - 1 since using cnt sign bit to stop
268269
$$Addr_wait_3 = '0000000000001' -- value are delay - 1 since using cnt sign bit to stop
@@ -273,7 +274,7 @@ $$Addr_wait_7 = '0000000000101'
273274
$$Addr_wait_8 = '0000000000110'
274275
$$Addr_wait_16 = '0000000001110'
275276
$$Addr_precharge_all = '0010000000000'
276-
$$Addr_mode_reg = '0001000110001'
277+
$$Addr_mode_reg = '0001000110011'
277278
$$Bank0 = '00'
278279
$$Bank1 = '01'
279280
$$Bank2 = '10'
@@ -284,7 +285,7 @@ $$DataZ = '0000000000000000'
284285
$$if ICARUS then
285286
$$ Addr_wait_R = Addr_wait_4
286287
$$else
287-
$$ Addr_wait_R = Addr_wait_3
288+
$$ Addr_wait_R = Addr_wait_5
288289
$$end
289290
$$bwidth = 4+2+13+2+16+1
290291
// CMD BANK ADDR DQM DATA DQEN
@@ -298,36 +299,36 @@ $$bwidth = 4+2+13+2+16+1
298299
// $bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
299300
// ^ 5
300301
// write in rowA
301-
$bwidth$b$CMD_PRECHARGE .. Bank0 .. AddrZ .. '00' .. DataZ .. '0'$,
302-
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
302+
// $bwidth$b$CMD_PRECHARGE .. Bank0 .. AddrZ .. '00' .. DataZ .. '0'$,
303+
// $bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
303304
$bwidth$b$CMD_ACTIVATE .. Bank0 .. AddrA_row .. '00' .. DataZ .. '0'$,
304305
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_2 .. '00' .. DataZ .. '0'$,
305-
$bwidth$b$CMD_WRITE .. Bank0 .. AddrA_col .. '00' .. '1010101010101010' .. '1'$,
306+
$bwidth$b$CMD_WRITE .. Bank0 .. AddrA_col .. '10' .. '0101010101010101' .. '1'$,
306307
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_8 .. '00' .. DataZ .. '0'$,
307-
// ^ 6
308+
// ^ 4
308309
// write in rowB
309-
$bwidth$b$CMD_PRECHARGE .. Bank1 .. AddrZ .. '00' .. DataZ .. '0'$,
310-
$bwidth$b$CMD_dummy_WAIT .. Bank1 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
311-
$bwidth$b$CMD_ACTIVATE .. Bank1 .. AddrB_row .. '00' .. DataZ .. '0'$,
312-
$bwidth$b$CMD_dummy_WAIT .. Bank1 .. Addr_wait_2 .. '00' .. DataZ .. '0'$,
313-
$bwidth$b$CMD_WRITE .. Bank1 .. AddrB_col .. '00' .. '1111111101110111' .. '1'$,
314-
$bwidth$b$CMD_dummy_WAIT .. Bank1 .. Addr_wait_8 .. '00' .. DataZ .. '0'$,
310+
// $bwidth$b$CMD_PRECHARGE .. Bank0 .. AddrZ .. '00' .. DataZ .. '0'$,
311+
// $bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
312+
// $bwidth$b$CMD_ACTIVATE .. Bank0 .. AddrB_row .. '00' .. DataZ .. '0'$,
313+
// $bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_2 .. '00' .. DataZ .. '0'$,
314+
$bwidth$b$CMD_WRITE .. Bank0 .. AddrB_col .. '10' .. '1010101010101010' .. '1'$,
315+
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_8 .. '00' .. DataZ .. '0'$,
315316
// ^ 2
316317
// read
317-
$bwidth$b$CMD_PRECHARGE .. Bank0 .. AddrZ .. '00' .. DataZ .. '0'$,
318-
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
319-
$bwidth$b$CMD_ACTIVATE .. Bank0 .. AddrA_row .. '00' .. DataZ .. '0'$,
320-
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_2 .. '00' .. DataZ .. '0'$,
318+
// $bwidth$b$CMD_PRECHARGE .. Bank0 .. AddrZ .. '00' .. DataZ .. '0'$,
319+
// $bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
320+
// $bwidth$b$CMD_ACTIVATE .. Bank0 .. AddrA_row .. '00' .. DataZ .. '0'$,
321+
// $bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_2 .. '00' .. DataZ .. '0'$,
321322
$bwidth$b$CMD_READ .. Bank0 .. AddrA_col .. '00' .. DataZ .. '0'$,
322323
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_R .. '00' .. DataZ .. '0'$,
323324
$bwidth$b$CMD_dummy_GET .. Bank0 .. AddrZ .. '00' .. DataZ .. '0'$,
324325
$bwidth$b$CMD_dummy_WAIT .. Bank0 .. Addr_wait_16 .. '00' .. DataZ .. '0'$,
325-
// ^ 8
326+
// ^ 4
326327
};
327-
$$n_instr = 5+6+6+8
328+
$$n_instr = 5+4+2+4
328329

329330
always_before {
330-
sdram_cle = ~reset;
331+
sdram_cle = 1;
331332
$$if not ULX3S_IO then
332333
sdram_cs = reg_sdram_cs;
333334
sdram_cas = reg_sdram_cas;

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