wip: sdram playground

Author: sylefeb

projects/sdram_playground/pll.v

@@ -5,18 +5,17 @@
 module pll
 (
     input clkin, // 25 MHz, 0 deg
-    output clkout0, // 50 MHz, 0 deg
-    output clkout1, // 25 MHz, 0 deg
-    output clkout2, // 100 MHz, 0 deg
-    output clkout3, // 100 MHz, 180 deg
-    output locked,
-    output reset
+    output clkout0, // 200 MHz, 0 deg
+    output clkout1, // 200 MHz, 0 deg
+    output clkout2, // 200 MHz, 0 deg
+    output clkout3, // 200 MHz, 180 deg
+    output locked
 );
 (* FREQUENCY_PIN_CLKI="25" *)
-(* FREQUENCY_PIN_CLKOP="50" *)
-(* FREQUENCY_PIN_CLKOS="25" *)
-(* FREQUENCY_PIN_CLKOS2="100" *)
-(* FREQUENCY_PIN_CLKOS3="100" *)
+(* FREQUENCY_PIN_CLKOP="200" *)
+(* FREQUENCY_PIN_CLKOS="200" *)
+(* FREQUENCY_PIN_CLKOS2="200" *)
+(* FREQUENCY_PIN_CLKOS3="200" *)
 (* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
 EHXPLLL #(
         .PLLRST_ENA("DISABLED"),
@@ -29,23 +28,23 @@ EHXPLLL #(
         .OUTDIVIDER_MUXD("DIVD"),
         .CLKI_DIV(1),
         .CLKOP_ENABLE("ENABLED"),
-        .CLKOP_DIV(12),
-        .CLKOP_CPHASE(5),
+        .CLKOP_DIV(3),
+        .CLKOP_CPHASE(1),
         .CLKOP_FPHASE(0),
         .CLKOS_ENABLE("ENABLED"),
-        .CLKOS_DIV(24),
-        .CLKOS_CPHASE(5),
+        .CLKOS_DIV(3),
+        .CLKOS_CPHASE(1),
         .CLKOS_FPHASE(0),
         .CLKOS2_ENABLE("ENABLED"),
-        .CLKOS2_DIV(6),
-        .CLKOS2_CPHASE(5),
+        .CLKOS2_DIV(3),
+        .CLKOS2_CPHASE(1),
         .CLKOS2_FPHASE(0),
         .CLKOS3_ENABLE("ENABLED"),
-        .CLKOS3_DIV(6),
-        .CLKOS3_CPHASE(8),
-        .CLKOS3_FPHASE(0),
+        .CLKOS3_DIV(3),
+        .CLKOS3_CPHASE(2),
+        .CLKOS3_FPHASE(4),
         .FEEDBK_PATH("CLKOP"),
-        .CLKFB_DIV(2)
+        .CLKFB_DIV(8)
     ) pll_i (
         .RST(1'b0),
         .STDBY(1'b0),
@@ -65,7 +64,4 @@ EHXPLLL #(
         .ENCLKOP(1'b0),
         .LOCK(locked)
 	);
-
-assign reset = ~locked;
-
 endmodule

projects/sdram_playground/sdram_ctrl_test.si

@@ -101,9 +101,9 @@ $$end
 
 $$if not ICARUS then
 uint1 rst(1);
-//clean_reset rstcond<@sdram_clock,!reset> (
-//  out   :> rst
-//);
+clean_reset rstcond<@sdram_clock,!reset> (
+  out   :> rst
+);
 $$else
 uint1 sdram_clock(0);
 $$end
@@ -160,7 +160,7 @@ $$if ULX3S then
     clkout2  :> sdram_clock, // controller
     clkout3  :> sdram_clk,   // chip
     locked   :> pll_lock,
-    reset    :> rst
+//    reset    :> rst
   );
 $$end
 $$if DE10NANO then
@@ -314,18 +314,30 @@ $$bwidth = 4+2+13+2+16+1
     $bwidth$b$CMD_WRITE         .. Bank0 .. AddrB_col           .. '10' .. '1010101010101010' .. '1'$,
     $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_8         .. '00' .. DataZ .. '0'$,
     // ^ 6
-    // read
+    // row-copy?
+    // -> activate A
     $bwidth$b$CMD_PRECHARGE     .. Bank0 .. AddrZ               .. '00' .. DataZ .. '0'$,
     $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_16        .. '00' .. DataZ .. '0'$,
     $bwidth$b$CMD_ACTIVATE      .. Bank0 .. AddrA_row           .. '00' .. DataZ .. '0'$,
+    $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_8         .. '00' .. DataZ .. '0'$,
+    // -> illegally activate B
+    $bwidth$b$CMD_PRECHARGE     .. Bank0 .. AddrZ               .. '00' .. DataZ .. '0'$,
+    // $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_16         .. '00' .. DataZ .. '0'$,
+    $bwidth$b$CMD_ACTIVATE      .. Bank0 .. AddrB_row           .. '00' .. DataZ .. '0'$,
+    $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_8         .. '00' .. DataZ .. '0'$,
+    // ^ 7
+    // read
+    $bwidth$b$CMD_PRECHARGE     .. Bank0 .. AddrZ               .. '00' .. DataZ .. '0'$,
+    $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_16        .. '00' .. DataZ .. '0'$,
+    $bwidth$b$CMD_ACTIVATE      .. Bank0 .. AddrB_row           .. '00' .. DataZ .. '0'$,
     $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_2         .. '00' .. DataZ .. '0'$,
-    $bwidth$b$CMD_READ          .. Bank0 .. AddrA_col           .. '00' .. DataZ .. '0'$,
+    $bwidth$b$CMD_READ          .. Bank0 .. AddrB_col           .. '00' .. DataZ .. '0'$,
     $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_R         .. '00' .. DataZ .. '0'$,
     $bwidth$b$CMD_dummy_GET     .. Bank0 .. AddrZ               .. '00' .. DataZ .. '0'$,
     $bwidth$b$CMD_dummy_WAIT    .. Bank0 .. Addr_wait_16        .. '00' .. DataZ .. '0'$,
     // ^ 8
   };
-  $$n_instr = 7+6+6+8
+  $$n_instr = 7+6+6+8+7 -- +1
 
   always_before {
     sdram_cle   = 1;