config.tcl

# OpenLane Config - CONSERVATIVE for first-pass success

set ::env(DESIGN_NAME) "tt_um_tensor_mac"
set ::env(VERILOG_FILES) [glob $::env(DESIGN_DIR)/src/*.v $::env(DESIGN_DIR)/src/*.sv]

# Clock - Conservative
set ::env(CLOCK_PERIOD) "20"
set ::env(CLOCK_PORT) "clk"

# Synthesis - Balanced
set ::env(SYNTH_STRATEGY) "AREA 0"
set ::env(SYNTH_MAX_FANOUT) 4  # Conservative

# Floorplan - LOOSE (avoid DRC)
set ::env(FP_CORE_UTIL) 40      # Low utilization = easier routing
set ::env(FP_ASPECT_RATIO) 1    # Square die
set ::env(FP_PDN_VPITCH) 30
set ::env(FP_PDN_HPITCH) 30

# Placement - Conservative
set ::env(PL_TARGET_DENSITY) 0.45  # Very loose

# Routing - Use all layers
set ::env(GLB_RT_MAXLAYER) 5

# DRC/LVS - Don't quit on errors (we'll fix iteratively)
set ::env(QUIT_ON_MAGIC_DRC) 0
set ::env(QUIT_ON_LVS_ERROR) 0

# Diode insertion for antenna fixes
set ::env(DIODE_INSERTION_STRATEGY) 4

# CTS
set ::env(RUN_CTS) 1