v5.0 Five Stage Pipelined Architecture

The core is now converted from FSM based implementation to a full 5 stage pipelined architecture.

New

• Added clock enables for pipeline control of each stage
• Added pipeline control logic on rv32i_core.v which includes detection and elimination of branch and data hazards
• Added returned instructions minstret and clk cycle count mcycle status on the output display of rv32i_soc_TB and test.sh for easier evaluation of pipeline efficiency
• rv32i_fetch.v = retrieves instruction from the memory [FETCH STAGE]

Pipeline Features

• 5 pipelined stages
• Separate data and instruction memory interface [Harvard architecture]
• Load instructions take a minimum of 2 clk cycles
• Taken branch and jump instructions take a minimum of 6 clk cycles [No Branch Prediction Used]
• Two consecutive instructions with data dependency take a minimum of 2 clk cycles. Nonconsecutive instructions with data dependency take a minimum of 1 clk cycle [Operation Forwarding used]
• All remaining instructions take a minimum of 1 clk cycle