Skip to content

Releases: akira2963753/Pipelined-RV32-SoC

Pipelined-RV32-Soc v1.0.0

31 May 01:23
@akira2963753 akira2963753
v1.0.0
ded74ad
This commit was created on GitHub.com and signed with GitHub’s verified signature.
GPG key ID: B5690EEEBB952194
Verified
Learn about vigilant mode.

Choose a tag to compare

View all tags
Pipelined-RV32-Soc v1.0.0 Pre-release
Pre-release

Release v1.0.0: Initial Release of 32-bit Pipelined RISC-V SoC by Marco

Key Features included in this release:

  • ISA Support: Implements the complete RV32I (Base Integer) and RV32M (Multiply/Divide) instruction sets, along with initial CSR support (mstatus, mtvec, mepc, mcause, rdcycle).

  • Advanced Pipeline Management: Built-in hardware mechanisms for data forwarding, load-use hazard stalling, and control hazard flushing to maintain structural integrity.

  • Dynamic Branch Prediction: Features a Branch Predictor utilizing a Branch Target Buffer (BTB) and a Branch History Table (BHT) with a 2-bit saturating counter.

  • Memory & Bus Interface: Includes a 2-way set-associative Level 1 Instruction Cache (I-Cache) and Data Cache (D-Cache), interfaced via an AXI4-Lite bus to Block RAM (BRAM).

  • Target Environment: Tailored for the Xilinx ZCU104 evaluation board and fully developed using Vivado 2025.1.

Automated Verification: Includes an automated Python-based test framework (Verify_Script.py) with a behavioral golden model. All 12 automated instruction verification test cases pass successfully.

Loading