Currently only the AXI bus is supported. Adding Wishbone would help open the OOT up to simulate more DSP implementations that already exist. Also adding this support is likely to bring up places where the interfaces can be structured to make the Host to HDL connection modular.
Currently only the AXI bus is supported. Adding Wishbone would help open the OOT up to simulate more DSP implementations that already exist. Also adding this support is likely to bring up places where the interfaces can be structured to make the Host to HDL connection modular.