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- Status: Open.#14 In gnuradio/gr-verilog;
Make it possible to control the base directory for a given module
enhancementNew feature or requestNew feature or requesthelp wantedExtra attention is neededExtra attention is neededStatus: Open.#10 In gnuradio/gr-verilog;Add example of generating VCD trace files for GTKWave
documentationImprovements or additions to documentationImprovements or additions to documentationenhancementNew feature or requestNew feature or requesthelp wantedExtra attention is neededExtra attention is neededStatus: Open.#9 In gnuradio/gr-verilog;Add support for optional TLAST signalling with tags
enhancementNew feature or requestNew feature or requesthelp wantedExtra attention is neededExtra attention is neededStatus: Open.#8 In gnuradio/gr-verilog;Add setting/passing parameters in HDL from GR/GRC
enhancementNew feature or requestNew feature or requesthelp wantedExtra attention is neededExtra attention is neededquestionFurther information is requestedFurther information is requestedStatus: Open.#7 In gnuradio/gr-verilog;Add gr-verilog to CGRAN
enhancementNew feature or requestNew feature or requestgood first issueGood for newcomersGood for newcomershelp wantedExtra attention is neededExtra attention is neededStatus: Open.#6 In gnuradio/gr-verilog;Check PyBOMBS support and recipes
enhancementNew feature or requestNew feature or requestgood first issueGood for newcomersGood for newcomershelp wantedExtra attention is neededExtra attention is neededStatus: Open.#5 In gnuradio/gr-verilog;Add support for cxxrtl as a simulation backend
enhancementNew feature or requestNew feature or requesthelp wantedExtra attention is neededExtra attention is neededStatus: Open.#4 In gnuradio/gr-verilog;Add template for Wishbone bus
enhancementNew feature or requestNew feature or requesthelp wantedExtra attention is neededExtra attention is neededStatus: Open.#3 In gnuradio/gr-verilog;Merge existing blocks into single block with templates
enhancementNew feature or requestNew feature or requestStatus: Open.#2 In gnuradio/gr-verilog;