Verilator is capable of generating VCD files with the states of logic lines for visualizing the execution of the HDL. GTKWave is a Free and Open Source Software application for working with these files.
https://github.com/gtkwave/gtkwave
An example of generating the VCD files is here.
https://zipcpu.com/blog/2017/06/21/looking-at-verilator.html
The GRC Block should have an option for enabling trace generation and a file path for where to generate it.
Verilator is capable of generating VCD files with the states of logic lines for visualizing the execution of the HDL. GTKWave is a Free and Open Source Software application for working with these files.
https://github.com/gtkwave/gtkwave
An example of generating the VCD files is here.
https://zipcpu.com/blog/2017/06/21/looking-at-verilator.html
The GRC Block should have an option for enabling trace generation and a file path for where to generate it.