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Add AMD FPGAs support and refactor code to abstract vendor specific FIFO names
1 parent c2d847f commit 739f9f8

14 files changed

Lines changed: 356 additions & 52 deletions

‎.gitignore‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,4 +9,11 @@ transcript
99

1010
# Test related
1111
obj_dir/
12-
regress_logs/
12+
regress_logs/
13+
14+
# Vivado generated
15+
.Xil/
16+
vivado*.log
17+
vivado*.jou
18+
compile_simlib.log
19+
.cxl.*

‎README.md‎

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -35,7 +35,7 @@ We support both **Verilator** and **ModelSim** simulation environments.
3535
#### Verilator
3636
*Note: Requires **Verilator 5.0 or later** (tested with version 5.048).*
3737

38-
Verilator simulations are compiled with behavioral FIFO models (`SIMULATION=1`):
38+
Verilator simulations are compiled with behavioral FIFO models (neither `QUARTUS_FIFO` nor `VIVADO_FIFO` is set):
3939
```bash
4040
make verilator [OPTIONS...]
4141
```
@@ -47,12 +47,13 @@ make verilator VERILATOR=$VERILATOR_ROOT/bin/verilator
4747
```
4848

4949
#### ModelSim
50-
ModelSim supports both behavioral simulation and actual Intel FPGA IPs/libraries.
50+
ModelSim supports behavioral simulation, Intel/Quartus FPGA IPs/libraries, and AMD/Xilinx/Vivado native/XPM FIFOs.
5151
```bash
5252
make modelsim [OPTIONS...]
5353
```
5454

55-
To run simulations with Quartus IPs, update your Quartus installation path on line 116 of [msim_setup.tcl](./test/sim/msim_setup.tcl) (Verified with Quartus version 23.2)
55+
* **Intel/Quartus FPGA IPs**: To run simulations with Quartus IPs, update your Quartus installation path on line 116 of [msim_setup.tcl](./test/sim/msim_setup.tcl) (Verified with Quartus version 23.2).
56+
* **AMD/Xilinx/Vivado IPs**: To run simulations with Vivado FIFOs (using XPM FIFO components), you must source your Vivado settings script (e.g., `source /path/to/Xilinx/Vivado/<version>/settings64.sh` or `settings.sh`) before launching the simulation. This is required because ModelSim compiles Vivado's XPM libraries on the fly using the `vivado` command line utility, which must be present in your `PATH`.
5657

5758
### Simulation Options
5859

@@ -62,18 +63,25 @@ To see the full list of options available, run the following command ([Descripti
6263
make help
6364
```
6465

65-
* **Behavioral Simulation (`SIMULATION=1`, Default)**: Uses fast, lightweight behavioral FIFO models.
66-
* **Intel FPGA IP Simulation (`SIMULATION=0`)**: Simulates the design using Intel FPGA IP blocks (`scfifo`, `dcfifo`).
66+
* **Behavioral Simulation (Default)**: Uses fast, lightweight behavioral FIFO models (neither `QUARTUS_FIFO=1` nor `VIVADO_FIFO=1` is set).
67+
* **Intel/Quartus FPGA IP Simulation (`QUARTUS_FIFO=1`)**: Simulates the design using Intel FPGA IP blocks (`scfifo`, `dcfifo`).
68+
* **AMD/Vivado FPGA IP Simulation (`VIVADO_FIFO=1`)**: Simulates the design using AMD/Xilinx native/XPM FIFOs.
6769

6870
### Simulation Examples
69-
Run a 4 $\times$ 4 Mesh topology simulation in ModelSim:
71+
Run a 4 $\times$ 4 Mesh topology simulation in ModelSim (Behavioral):
7072
```bash
7173
make modelsim TOPOLOGY=mesh NUM_ROWS=4 NUM_COLS=4
7274
```
7375

74-
Run a clock-crossing simulation using Intel FPGA IPs in ModelSim:
76+
Run a clock-crossing simulation using Quartus/Intel FPGA IPs in ModelSim:
7577
```bash
76-
make modelsim SIMULATION=0 CLKCROSS_FACTOR=2
78+
make modelsim QUARTUS_FIFO=1 CLKCROSS_FACTOR=2
79+
```
80+
81+
Run a clock-crossing simulation using Vivado/AMD FPGA IPs in ModelSim:
82+
```bash
83+
source /path/to/Xilinx/Vivado/2024.1/settings64.sh # Load Vivado settings first!
84+
make modelsim VIVADO_FIFO=1 CLKCROSS_FACTOR=2
7785
```
7886

7987
## NoC Parameterization

‎src/axis_serdes_shims.sv‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -342,7 +342,7 @@ module axis_clkcross_shim_in #(
342342

343343
// Instantiations
344344
// Destination + Tail buffer
345-
dcfifo_agilex7 #(
345+
dcfifo #(
346346
.WIDTH (TDEST_WIDTH + 1),
347347
.DEPTH (BUFFER_DEPTH),
348348
.EXTRA_SYNC_STAGES (EXTRA_SYNC_STAGES),
@@ -363,7 +363,7 @@ module axis_clkcross_shim_in #(
363363
// Data buffer
364364
generate begin: data_fifo_gen
365365
if (SERIALIZATION_FACTOR == 1) begin
366-
dcfifo_agilex7 #(
366+
dcfifo #(
367367
.WIDTH (TDATA_WIDTH),
368368
.DEPTH (BUFFER_DEPTH),
369369
.EXTRA_SYNC_STAGES (EXTRA_SYNC_STAGES),
@@ -381,7 +381,7 @@ module axis_clkcross_shim_in #(
381381
.wrfull (data_buffer_wrfull)
382382
);
383383
end else begin
384-
dcfifo_mixed_width_agilex7 #(
384+
dcfifo_mixed_width #(
385385
.WIDTH_IN (TDATA_WIDTH),
386386
.WIDTH_OUT (FLIT_WIDTH),
387387
.DEPTH (BUFFER_DEPTH),
@@ -484,7 +484,7 @@ module axis_clkcross_shim_out #(
484484

485485
// Instantiations
486486
// Destination + Tail buffer
487-
dcfifo_agilex7 #(
487+
dcfifo #(
488488
.WIDTH (TDEST_WIDTH + 1),
489489
.DEPTH (BUFFER_DEPTH),
490490
.EXTRA_SYNC_STAGES (EXTRA_SYNC_STAGES),
@@ -505,7 +505,7 @@ module axis_clkcross_shim_out #(
505505
// Data buffer
506506
generate begin: data_buffer_gen
507507
if (SERIALIZATION_FACTOR == 1) begin
508-
dcfifo_agilex7 #(
508+
dcfifo #(
509509
.WIDTH (FLIT_WIDTH),
510510
.DEPTH (BUFFER_DEPTH * SERIALIZATION_FACTOR),
511511
.EXTRA_SYNC_STAGES (EXTRA_SYNC_STAGES),
@@ -524,7 +524,7 @@ module axis_clkcross_shim_out #(
524524
.wrusedw(data_buffer_wrusedw)
525525
);
526526
end else begin
527-
dcfifo_mixed_width_agilex7 #(
527+
dcfifo_mixed_width #(
528528
.WIDTH_IN (FLIT_WIDTH),
529529
.WIDTH_OUT (TDATA_WIDTH),
530530
.DEPTH (BUFFER_DEPTH * SERIALIZATION_FACTOR),
@@ -600,7 +600,7 @@ module axis_shim_in #(
600600
send_out <= buffer_rdreq;
601601
end
602602

603-
fifo_agilex7 #(
603+
fifo #(
604604
.WIDTH (TDATA_WIDTH + TDEST_WIDTH + 1),
605605
.DEPTH (BUFFER_DEPTH),
606606
.FORCE_MLAB (FORCE_MLAB))
@@ -662,7 +662,7 @@ module axis_shim_out #(
662662
assign credit_out = ((credit_count < FLIT_BUFFER_DEPTH) || send_in) &&
663663
((credit_count < (BUFFER_DEPTH - buffer_usedw)) || (axis_tready & axis_tvalid));
664664

665-
fifo_agilex7 #(
665+
fifo #(
666666
.WIDTH (TDATA_WIDTH + TDEST_WIDTH + 1),
667667
.DEPTH (BUFFER_DEPTH),
668668
.SHOWAHEAD ("ON"),

src/fifos/dcfifo_agilex7.sdc renamed to src/fifos/dcfifo.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,4 +82,4 @@ foreach each_inst $inst_list {
8282

8383
}
8484
}
85-
apply_sdc_pre_dcfifo dcfifo_agilex7
85+
apply_sdc_pre_dcfifo dcfifo

src/fifos/dcfifo_agilex7.sv renamed to src/fifos/dcfifo.sv

Lines changed: 69 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
// synopsys translate_off
1616
`timescale 1 ps / 1 ps
1717
// synopsys translate_on
18-
module dcfifo_agilex7 #(
18+
module dcfifo #(
1919
parameter WIDTH = 512,
2020
parameter DEPTH = 8,
2121
parameter EXTRA_SYNC_STAGES = 0,
@@ -51,7 +51,72 @@ module dcfifo_agilex7 #(
5151
// synopsys translate_on
5252
`endif
5353

54-
`ifndef SIMULATION
54+
`ifdef QUARTUS_FIFO
55+
`ifdef VIVADO_FIFO
56+
initial begin
57+
$fatal(1, "Both QUARTUS_FIFO and VIVADO_FIFO are defined.");
58+
end
59+
`endif
60+
`endif
61+
62+
`ifdef VIVADO_FIFO
63+
localparam XILINX_DEPTH = (DEPTH < 16) ? 16 : DEPTH;
64+
localparam CDC_STAGES_REQ = 4 + EXTRA_SYNC_STAGES;
65+
localparam CDC_STAGES_CLAMPED = (CDC_STAGES_REQ < 2) ? 2 : ((CDC_STAGES_REQ > 8) ? 8 : CDC_STAGES_REQ);
66+
localparam XILINX_CDC_SYNC_STAGES = (XILINX_DEPTH == 16 && CDC_STAGES_CLAMPED >= 5) ? 4 : CDC_STAGES_CLAMPED;
67+
68+
wire [$clog2(XILINX_DEPTH) : 0] xil_wrusedw;
69+
assign wrusedw = xil_wrusedw[$clog2(DEPTH):0];
70+
71+
wire xil_wrfull;
72+
wire xil_rdempty;
73+
wire wr_rst_busy;
74+
wire rd_rst_busy;
75+
76+
assign wrfull = xil_wrfull || wr_rst_busy;
77+
assign rdempty = xil_rdempty || rd_rst_busy;
78+
79+
xpm_fifo_async #(
80+
.FIFO_MEMORY_TYPE (FORCE_MLAB ? "distributed" : "auto"),
81+
.FIFO_WRITE_DEPTH (XILINX_DEPTH),
82+
.WRITE_DATA_WIDTH (WIDTH),
83+
.READ_DATA_WIDTH (WIDTH),
84+
.READ_MODE ((SHOWAHEAD == "ON") ? "fwft" : "std"),
85+
.FIFO_READ_LATENCY ((SHOWAHEAD == "ON") ? 0 : 1),
86+
.CDC_SYNC_STAGES (XILINX_CDC_SYNC_STAGES),
87+
.ECC_MODE ("no_ecc"),
88+
.USE_ADV_FEATURES ("0505"),
89+
.WR_DATA_COUNT_WIDTH ($clog2(XILINX_DEPTH) + 1)
90+
) xpm_fifo_async_inst (
91+
.wr_clk (wrclk),
92+
.rd_clk (rdclk),
93+
.rst (aclr),
94+
.din (data),
95+
.wr_en (wrreq),
96+
.rd_en (rdreq),
97+
.dout (q),
98+
.empty (xil_rdempty),
99+
.full (xil_wrfull),
100+
.wr_data_count (xil_wrusedw),
101+
.sleep (1'b0),
102+
.injectsbiterr (1'b0),
103+
.injectdbiterr (1'b0),
104+
.sbiterr (),
105+
.dbiterr (),
106+
.rd_rst_busy (rd_rst_busy),
107+
.wr_rst_busy (wr_rst_busy),
108+
.almost_full (),
109+
.almost_empty (),
110+
.prog_full (),
111+
.prog_empty (),
112+
.wr_ack (),
113+
.overflow (),
114+
.underflow (),
115+
.data_valid (),
116+
.rd_data_count ()
117+
);
118+
`elsif QUARTUS_FIFO
119+
55120
wire [WIDTH-1:0] sub_wire0;
56121
wire sub_wire1;
57122
wire sub_wire2;
@@ -90,6 +155,7 @@ module dcfifo_agilex7 #(
90155
dcfifo_component.use_eab = "ON",
91156
dcfifo_component.write_aclr_synch = "ON",
92157
dcfifo_component.wrsync_delaypipe = 4 + EXTRA_SYNC_STAGES;
158+
93159
`else
94160

95161
localparam ADDR_WIDTH = $clog2(DEPTH);
@@ -184,6 +250,6 @@ module dcfifo_agilex7 #(
184250

185251
`endif
186252

187-
endmodule
253+
endmodule: dcfifo
188254

189255

src/fifos/dcfifo_mixed_width_agilex7.sdc renamed to src/fifos/dcfifo_mixed_width.sdc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,4 +87,4 @@ foreach each_inst $inst_list {
8787

8888
}
8989
}
90-
apply_sdc_pre_mw_dcfifo dcfifo_mixed_width_agilex7
90+
apply_sdc_pre_mw_dcfifo dcfifo_mixed_width

src/fifos/dcfifo_mixed_width_agilex7.sv renamed to src/fifos/dcfifo_mixed_width.sv

Lines changed: 69 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515
// synopsys translate_off
1616
`timescale 1 ps / 1 ps
1717
// synopsys translate_on
18-
module dcfifo_mixed_width_agilex7 #(
18+
module dcfifo_mixed_width #(
1919
parameter WIDTH_IN = 512,
2020
parameter WIDTH_OUT = 128,
2121
parameter DEPTH = 8,
@@ -51,7 +51,72 @@ module dcfifo_mixed_width_agilex7 #(
5151
// synopsys translate_on
5252
`endif
5353

54-
`ifndef SIMULATION
54+
`ifdef QUARTUS_FIFO
55+
`ifdef VIVADO_FIFO
56+
initial begin
57+
$fatal(1, "Both QUARTUS_FIFO and VIVADO_FIFO are defined.");
58+
end
59+
`endif
60+
`endif
61+
62+
`ifdef VIVADO_FIFO
63+
localparam XILINX_DEPTH = (DEPTH < 16) ? 16 : DEPTH;
64+
localparam CDC_STAGES_REQ = 4 + EXTRA_SYNC_STAGES;
65+
localparam CDC_STAGES_CLAMPED = (CDC_STAGES_REQ < 2) ? 2 : ((CDC_STAGES_REQ > 8) ? 8 : CDC_STAGES_REQ);
66+
localparam XILINX_CDC_SYNC_STAGES = (XILINX_DEPTH == 16 && CDC_STAGES_CLAMPED >= 5) ? 4 : CDC_STAGES_CLAMPED;
67+
68+
wire [$clog2(XILINX_DEPTH) : 0] xil_wrusedw;
69+
assign wrusedw = xil_wrusedw[$clog2(DEPTH):0];
70+
71+
wire xil_wrfull;
72+
wire xil_rdempty;
73+
wire wr_rst_busy;
74+
wire rd_rst_busy;
75+
76+
assign wrfull = xil_wrfull || wr_rst_busy;
77+
assign rdempty = xil_rdempty || rd_rst_busy;
78+
79+
xpm_fifo_async #(
80+
.FIFO_MEMORY_TYPE ("auto"),
81+
.FIFO_WRITE_DEPTH (XILINX_DEPTH),
82+
.WRITE_DATA_WIDTH (WIDTH_IN),
83+
.READ_DATA_WIDTH (WIDTH_OUT),
84+
.READ_MODE ((SHOWAHEAD == "ON") ? "fwft" : "std"),
85+
.FIFO_READ_LATENCY ((SHOWAHEAD == "ON") ? 0 : 1),
86+
.CDC_SYNC_STAGES (XILINX_CDC_SYNC_STAGES),
87+
.ECC_MODE ("no_ecc"),
88+
.USE_ADV_FEATURES ("0505"),
89+
.WR_DATA_COUNT_WIDTH ($clog2(XILINX_DEPTH) + 1)
90+
) xpm_fifo_async_inst (
91+
.wr_clk (wrclk),
92+
.rd_clk (rdclk),
93+
.rst (aclr),
94+
.din (data),
95+
.wr_en (wrreq),
96+
.rd_en (rdreq),
97+
.dout (q),
98+
.empty (xil_rdempty),
99+
.full (xil_wrfull),
100+
.wr_data_count (xil_wrusedw),
101+
.sleep (1'b0),
102+
.injectsbiterr (1'b0),
103+
.injectdbiterr (1'b0),
104+
.sbiterr (),
105+
.dbiterr (),
106+
.rd_rst_busy (rd_rst_busy),
107+
.wr_rst_busy (wr_rst_busy),
108+
.almost_full (),
109+
.almost_empty (),
110+
.prog_full (),
111+
.prog_empty (),
112+
.wr_ack (),
113+
.overflow (),
114+
.underflow (),
115+
.data_valid (),
116+
.rd_data_count ()
117+
);
118+
`elsif QUARTUS_FIFO
119+
55120
wire [WIDTH_OUT-1:0] sub_wire0;
56121
wire sub_wire1;
57122
wire sub_wire2;
@@ -93,6 +158,7 @@ module dcfifo_mixed_width_agilex7 #(
93158
dcfifo_mixed_widths_component.use_eab = "ON",
94159
dcfifo_mixed_widths_component.write_aclr_synch = "ON",
95160
dcfifo_mixed_widths_component.wrsync_delaypipe = 4 + EXTRA_SYNC_STAGES;
161+
96162
`else
97163

98164
localparam RATIO = (WIDTH_IN >= WIDTH_OUT) ? (WIDTH_IN / WIDTH_OUT) : (WIDTH_OUT / WIDTH_IN);
@@ -247,7 +313,6 @@ module dcfifo_mixed_width_agilex7 #(
247313

248314
`endif
249315

250-
251-
endmodule
316+
endmodule: dcfifo_mixed_width
252317

253318

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