This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.
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Jun 28, 2026 - C++
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amba-apb
Here are 15 public repositories matching this topic...
This Repository contains the Implementation of the AMBA APB4 Protocol with Verilog, featuring an APB master, APB slave with cache memory, and comprehensive testbenches. Includes scripts for fast simulation and synthesis using QuestaSim, Vivado and Quartus Prime
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Sep 5, 2024 - Verilog
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
verification matrix-multiplication verilog systemverilog questasim logic-design sva systolic-arrays amba-apb functional-coverage chip-design
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Jun 26, 2024 - Verilog
Design and verification of the Advanced Peripheral Bus (APB) protocol using Verilog. Includes Verilog modules for APB operations and a testbench for verifying functionality and compliance with protocol standards.
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Jul 28, 2025 - Verilog
Design of a system bus architecture - Team Project @ ENTC UoM
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Sep 7, 2022 - Verilog
This repo will contain the Verilog code implementation of various protocols that fall within AMBA protocol family such as APB, AHB, AXI and so on. I will implement it in parallel with learning theory. If possible I will also use UVM and system verilog to verify the functionality of the code once I finish learning system verilog and concepts of uvm
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Dec 9, 2024 - Verilog
Advanced Pheripheral Bus design using verilog HDL
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Sep 7, 2021 - Verilog
SymbiYosys (sby) Formal Verification
verification verilog formal-methods formal-verification verilog-hdl yosys wishbone verilator apb wishbone-bus amba-apb symbiyosys sby wishbone-master
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Feb 22, 2025 - F#
32-bit single-cycle RISC-V SoC in SystemVerilog featuring an APB interconnect, UART, PWM, Timer peripherals, and a Java-based control-word generator for memory-mapped peripheral configuration.
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Jun 27, 2026 - SystemVerilog
Smart Farm Sensor System with AMBA APB Interface my RISC-V
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Jul 25, 2025 - SystemVerilog
A synthesizable UART design with an AMBA APB3 slave interface. Verified using SystemVerilog, Assertions (SVA), and functional coverage.
coverage assertions uart systemverilog sva apb functional-verification amba-apb functional-coverage systemverilog-assertions apb-protocol uart-apb-interfacing
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Jun 20, 2026 - SystemVerilog
APB RAM RTL design with full UVM-based verification using constrained-random testing.
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Feb 4, 2026 - SystemVerilog
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