Headless, event-driven simulation of the German railway (Deutsche Bahn) network — a research tool for studying delay propagation, capacity bottlenecks, and dispatching strategies across macroscopic, mesoscopic, and microscopic scales.

porject from designing with VHDL course. Includes, FSM (finite state machine), next state logic,seven-segment-display-decode, full adder, flip flops, D_flip-flops, ripple carry adder, full adder, half adder, delay propagation