Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

A ZipCPU SoC for the Nexys Video board supporting video functionality

A 5-stage pipelined RV32IMF RISC-V SoC optimized for FPGA (Nexys Video/4-DDR). Features a custom IEEE-754 FPU, interrupt-driven UART, and various peripherals.

Slaves for AXI-lite interface

VeeRwolf (a platform for the VeeR family of RISC-V cores) for Nexys Video Board: https://github.com/chipsalliance/VeeRwolf

A guide on how to write basic FPGA programming in VHDL and its implementation. This targeted the one who has no experience with Vivado.

Nexys Video FPGA sensor-fusion HUD integrating Pcam 5C camera input, sonar acquisition, CDC-safe telemetry snapshots, HDMI compositing, OLED telemetry, and debug outputs.

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Predict future robot states and task progress using a video-generative value model to improve reinforcement learning performance.