OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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Jul 1, 2026 - Verilog
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timing-analysis
Here are 57 public repositories matching this topic...
🟢 Super-fast, tiny C/C++ tracing with printf look-and-feel, even in interrupts ⚡, plus real-time PC logging 💻
c debugging golang real-time embedded compression encryption monitoring serial tool logging printf instrumentation trace diagnostics rtos multi-language-support timing-analysis data-recording time-measurement
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Jul 1, 2026 - C
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jul 1, 2026 - Verilog
AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
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Mar 9, 2024 - C++
Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption
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Aug 25, 2023 - Python
This is a tutorial on standard digital design flow
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May 24, 2021 - Tcl
This repository contains code and data for "Tik-Tok: The Utility of Packet Timing in Website Fingerprinting Attacks" paper, published in PETS 2020.
machine-learning privacy deep-learning website-fingerprinting tor-network attacks privacy-enhancing-technologies timing-analysis tik-tok
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Jun 16, 2026 - Python
Gate-level timing estimation toolkit
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Apr 11, 2022 - Shell
A NuGet that allows you to use a Azure DevOps Service Hook to track workitems changes in a simply and detailed way.
tracker devops agile azure scrum columns team trackers workitem agile-development timing-analysis azure-devops azuredevops team-performance
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Aug 18, 2025 - C#
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
characterization power-analysis hspice spice-simulator vlsi-circuits timing-analysis vlsi-design vlsi-cad
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Feb 13, 2020 - C++
Evaluation Framework for Self-Suspending Task Systems
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Feb 24, 2026 - Python
GG for Arduino is a serial console library. It also contains various functions for implementing the console, for example printf(). You can implement a command line interface on your Arduino and add your own commands. This library contains built-in commands that allow memory access and timing analysis.
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Nov 26, 2023 - C
Compiler backend from packing to bitstream generation.
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Dec 3, 2024 - C++
Engineering notes and reproducible FPGA examples from real-world development, including RTL design, simulation, verification and debugging.
fpga zynq matlab rtl verilog chinese xilinx vivado digital-signal-processing rapidio engineering-notes axi-stream timing-analysis fpga-tutorial
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Jun 26, 2026 - Verilog
Detect side channels with statistically rigorous methods.
cryptography side-channel timing-attacks security-tools security-research side-channel-attacks timing-analysis side-channel-analysis
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Apr 22, 2026 - Rust
SerDes RTL design, verification using UVM and Physical design.
fsm serdes synthesis piso-shift-register highspeed encoder-decoder sipo timing-analysis physical-design place-and-route
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May 26, 2024 - Verilog
ttcp is a simple Rust-coded tool to measure TCP timing and detect anomalies.
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Oct 17, 2025 - Rust
Academic-grade Worst-Case Execution Time analysis using LLVM infrastructure for embedded systems and real-time applications
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Nov 4, 2025 - TypeScript
RTAS 2021 - Artifact Evaluation for "Timing Analysis of Asynchronized Distributed Cause-Effect Chains"
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Mar 26, 2021 - Python
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