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wcet

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Performance benchmarking for deterministic ML inference. Measures latency, throughput, WCET with cryptographic verification of bit-identity across platforms. 11,840 test assertions. Pure C99, no dynamic allocation. Part of the certifiable-* ecosystem for safety-critical AI.

  • Updated Mar 29, 2026
  • C

Stoic-V: a deterministic RV32IM + Zba/Zbb/Zbs + Zicsr (M-mode) RISC-V soft core in SystemVerilog. No caches, speculation, or branch prediction, so timing is operand-independent and WCET is statically analysable. Drop-in replacement for the AMD MicroBlaze-V via the LMB v10 interface; closes 250 MHz on UltraScale+.

  • Updated Jun 13, 2026
  • SystemVerilog

A cycle-accurate simulation research comparing deterministic execution on the Patmos processor against a conventional speculative CPU, demonstrated through a real-time obstacle avoidance scenario with live WCET, jitter, and deadline analysis.

  • Updated May 5, 2026
  • TypeScript

Portable, deterministic C++20 control library for industrial autonomy: PID to MPC to adaptive controllers, safety-gated and production-ready.

  • Updated Oct 10, 2025
  • C++

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